1. Field of the Invention
The present invention relates to the field of programmable logic devices and more specifically to improving the performance of EPROM arrays.
2. Related Application
This application relates to copending U.S. patent application Ser. No. 292,462, filed Dec. 30, 1988, and entitled "Shift Register Programming for a Programmable Logic Device."
3. Prior Art
The manufacture and use of erasable programmable ready-only-memories (EPROMs) are well-known in the prior art. More recently, EPROM devices have been combined with programmable logic arrays to provide devices which are commonly known as programmable logic devices (PLDs). In many instances, PLDs are also erasable and have been referred to as erasable programmable logic devices (EPLDs).
Generally, a memory element for each device is configured into an array, wherein each input to the PLD is divided into an inverting and a non-inverting inputs and in which each input forms a pair of row lines of the memory array matrix. The row lines are typically referred to as word lines. Each column of memory cells are coupled together by column lines which are typically referred to as bit lines. These bit lines of the array are used to provide the output from the memory array. These bit line outputs are thus NOR gates, but are referred to through Boolean transformation as n-term product terms. These product outputs are then logically OR'ed to provide a sum of the products. The technique of using a memory array wherein inputs are provided on the various row lines and the technique of summing the product outputs from the columns of the array are well known in the prior art. Such examples are taught by two U.S. patents to Hartmann et al. (U.S. Pat. Nos. 4,609,986 and 4,617,479) as well as a patent to Birkner et al. (U.S. Pat. No. 4,124,899).
Although a variety of PLD devices are known in the prior art, these devices require the input lines to be coupled to access the EPROM cell. Generally, the input lines are coupled to the control gate of a floating gate EPROM cell, wherein the output of the cell is dependent on the programmed or unprogrammed (erased) state of the EPROM cell of the floating gate, and on the state of the input signal if in the erased state. If a signal path is traced from the input to the output of the memory array, it is noted that the EPROM cell resides within that signal path. That is, the input signal must access the EPROM before an output can be obtained from the PLD. The presence of the EPROM cell in the signal path inhibits the performance, notably speed and power performance, of the PLD. This results from the need to access a given EPROM cell before an output can be obtained and the given EPROM cell can be accessed only after the input signal is present at the control gate.
It is appreciated then that an improvement to the performance of a PLD can be achieved if the memory cell can be removed from the signal path of the device.